"http://www.w3.org/TR/xhtml1/DTD/xhtml1- .diff_header {background-color:#e0e0e0} td.diff_header {text-align:right} .diff_next {background-color:#c0c0c0} .diff_add {background-color:#aaffaa} .diff_chg {background-color:#ffff77} .diff_sub {background-color:#ffaaaa}

ex1a_tb.v:1: error: `timescale directive can not be inside a module definition.
ex1a_tb.v:2: syntax error
C:\Users\–ìXŽR— É\Desktop\VerilogSimulation_new\EA\a\ex1\170441082ex1.v:5: error: Invalid module instantiation
a.out: Unable to open input file.

	student			correct
t			t	1	/* ex1 ‰ð“š—á */
	1	module AND_OR_EX1( A, B, C, Y );		2	module AND_OR_EX1(A, B, C, Y);
	2	input A, B, C;		3	input A, B, C;
	3	output Y;		4	outpu t Y;
	4	assign Y = ( A & B ) \| C;		5	assign Y = (A & B) \| C;
	5	enmodule		6	endmodule

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